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Report After Setting an Output Delay

The timing report after setting an output delay of 2 ns on output port d using the set output delay command is shown below. The output delay specified on port d implies that the path must account for a delay of 2 ns, external to the Q pin of d reg. In other words, data must arrive 2 ns earlier at the output port d in order to meet timing requirements defined by flip-flops external to the port d. [Pg.106]

Report timing -path full -delay max -max paths 1 Design timing [Pg.107]

Startpoint d reg (rising edge-triggered flip-flop clocked by elk) Endpoint d (output port clocked by elk) [Pg.107]

Note the output external delay specified in the timing report. [Pg.107]

2 Timing Report after setting an input delay constraint [Pg.108]


See other pages where Report After Setting an Output Delay is mentioned: [Pg.106]   


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