Poly Si CMP for NAND Flash Memory

FIGURE 6.8 (a) Cross-sectional SEM image of a 90-nm NAND-flash memory-cell without CMP. (b) Cross-sectional TEM image of a sub-60 nm structure with interpoly ONO dielectrics. 

Missing electron state is the erase. Programming and erasing are formed according to the size of Vjh of cell transistor. 

Especially, the height of floating gate should be controlled through the CMP process because that greatly influences word-line and bit-line cells. 

To achieve the isolated poly floating gate, the polishing should be stopped at the oxide film. Therefore, the poly-to-oxide removal selectivity is the most important factor for the poly isolation CMP process. Poly isolation CMP without selectivity induces dishing and rugged topography on surfaces, which result in deterioration in the quality of interlayers in the device. 

FIGURE 6.9 (See color insert) Schematic process flow of the poly isolation CMP process. 

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