Output ripple

Ultimately, the designer must try-out the final design and check the output ripple voltage and the temperature rise of each capacitor. 

Maximum output current Output ripple voltage Output regulation ... 

Once again, high and low frequency limiting must be introduced on the control IC in order to minimize output ripple voltage and zero switching loss conditions. 

So, why not use an elko OK, it has a higher ESR. It gives higher output ripple. Granted ... 

The ESL adds AV = Vesl to the output ripple, where Ves = Vesl on + Vesl off)... 

The value of the inductor may be increased above the minimum recommended value to reduce input and output ripple. However, once the ripple current is less than 20% of the average current in the inductor, the benefit to output ripple becomes minimal. 

The equivalent series resistance (ESR) and equivalent series inductance (ESL) of the output capacitor substantially control the output ripple. Use an output capacitor with low ESR and ESL. Surface mount Tantalums, surface mount polymer electrolytic and polymer electrolytic and polymer Tantalum, Sanyo OS-CON, or multilayer ceramic capacitors are recommended. Electrolytic capacitors are not... 

Author s Comments The first company representative seems to have dished out the stock reply on reducing output ripple in conventional (PWM) regulators. But his second point is a fairly good run-down on capacitors in general. However, the 2621 is a hysteretic controller and therefore depends on output ripple to behave. So the advice doesn t really apply. 

The results of the breadboard waveforms and the IsSpice waveforms are compared side by side in Figs. 4.15 and 4.16. Figure 4.15 shows the output ripple voltage at the top, with the inductor voltage at the bottom. Figure 4.16 shows the oscillator frequency at the top, with the... 

Figure 4.15a IsSpice LM78S40 waveforms (top, output ripple bottom, inductor voltage).

A precarious dilemma results when creating a model that can accurately depict a transient response of the converter as well as the output ripple. The ESR of capacitor C2 is a function of frequency. When simulating the output ripple of the converter, the frequency is essentially constant, approximately 25 kHz. However, when the converter... 

Figure 4.31 IsSpice UA723 buck regulator output ripple.

In correlating to the transient response, many difficulties arose. The ESR of C2 determines the magnitude of the transient response, as well as the frequency of the output ripple. Varying the ESR of C2 varies the period of the output ripple in which the transient occurred. A larger magnitude of the transient response corresponds to the transient occurring while the transistor is conducting, which indicates that the simulation results are dependent on when the transient occurs. 

The transient domain model shown in Fig. 4.33 was used to measure output ripple voltage, transient response, gate voltage, and inductor current. This model properly predicts the cycle-by-cycle switching effects of the regulator. 

Figure 4.40 shows the simulated output ripple voltage, while Fig. 4.41 shows the simulated output voltage ripple. The measured transient response is shown in Fig. 4.42, while the simulated transient response is shown in Fig. 4.43. 

M = -1.145M Figure 4.40 Simulated output ripple. 

The load at this condition was 200 2. The results of the IsSpice simulations were very similar to the breadboard results, as shown in Fig. 10.23, especially the output ripple in Fig. 10.24. 

The measurements for the output ripple at a load of 200 k 2 for each of the simulators, and the breadboard was also summarized in Table 10.6. 

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