NanoCell architecture

Furthermore, as a check of defect tolerance, large, multiple-switch NanoCells were tested for defect tolerance through the SPICE interface. With all switches in the "on" position, the cell showed NAND logic with on-to-off output current thresholds of approximately 20 1. Switches were then chosen at random and set to the "off position and the cell was evaluated periodically (data not shown). The average NanoCell tested had 1826 switches, and >60% of these switches could be turned to the off non-conducting state before the cell lost NAND functionality with the minimum output on-to-off ratio set-point of 10 1. This indicates a high tolerance for numerous faults in the NanoCell architecture. 

Figure 6.36 This is a molecular electronics architecture using 4-pin NanoCells. The picture on the left depicts a four bit adder comprised of comer turns (1 ), half adders ( ) and XORs (the little shield symbols). Each sh e represens a different clock cycle. The figure on the right illustrates four NanoCells wired together.

Figure 6.37 This is an architecture that includes bistable latches. The side view demonstrates the bistable latch outside the NanoCell. The figures on the right illustrate a potential process for constructing such a NanoCell.

Figure 6.45 Depicted here is a NanoCell trained as a half adder connected to a NanoCell trained as a comer turn. The architecture that uses these cells is displayed in Figure 6.36. The input and output signals are shown in Figure 6.46.

The advances made by the computer architecture group have enabled us to offer valuable advice to the rest of the team. We are able to suggest the most easily trainable NanoCells. We have also recommended that the NanoCell be reduced in size from that shown in Figure 6.1 to that shown in Figure 6.39. 

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