Logic Restructuring as an Aid to Physical Retiming

Increasing the optimization scope and window sizes can help avoid local minima in the solution space that trap individual, local transformations. Additionally, 

Papa and I. L. Markov, Multi-Objective Optimization in Physical Synthesis of Integrated Circuits, Lecture Notes in Electrical Engineering 166, 

RETIMING helps select combinational gates for CLONING CLONING creates new opportunities for RETIMING (see Fig. 7.2) 

RETIMING relocates netlist registers, causing new PLACEMENT 

PLACEMENT changes interconnect delays used in STA Register PLACEMENT after retiming is performed based on STA 

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