Lock-on time

Fig. 6.2. Sketch of the time response to a voltage pulse Vp > and to interrogating voltage pulses V < for (a) a threshold switch and (b) a memory switch. Switching from OFF to ON occurs after a delay time tj. The memory is SET after a lock-on time interval LO after switching. The threshold switch (a) returns to OFF after the end of the Vp pulse. The memory switch (b) requires a RESET current pulse to return to the high resistance OFF state.

The electrical response of a typical memory switch is shown in Figures 6.1(d) and 6.2(b). The switching process and filamentary conduction of a memory switch is essentially the same as tha of the threshold switch. In fact, when the voltage is removed immediately after switching, the memory switch reverts to the OFF state. On the other hand, the memory switch retains its conductive state after it has been kept in this state (5-10 mA current level) for about 10" sec, the lock-on time LO, to SET the memory state. Once in the ON-state, the device is turned off by the application of a short, intense RESET current pulse, typically of 5 /x sec duration and 120 mA current. The impedance of the device can be ascertained by a low level (0.5 V, 5 ju sec) read pulse as sketched in Figure 2(b). A typical SET — RESET sequence with interrogating READ pulses is shown in Figure 6.13 (Bunton and Quilliam (1972)). 18 traces are superimposed in this... 

---