Honeywells V-Synth System

Honeywell s V-Synth (VHDL-Synthesis) System decomposes VHDL descriptions into simple statements, optimizes those statements with compiler-like transformations, schedules the operations into states, and then passes the resulte to the MIMOLA Synthesis System to complete the design process. See also Univ, of Kiel s MIMOLA System. 

Uses a process graph, which represents the behavior as a set of nodes, or blocks, connected by directed arcs. Each block contains a set of statements, with each statement either a simple assignment statement (one operation, and at most two operators), or a simple (IF...THEN...ELSE) conditional statement. If a conditional statement is included, it must be the last statement in the block. 

Compiler-like transformations, including constant folding, code motion, global common-subexpression elimination, expression factoring, and redundant code elimination. 

Uses back-substitution to rewrite the statements in each block into a form where each assignment statement has an output variable on the left-hand side, and variables other than output variables on the right-hand side. The resulting statements can then be executed in any sequence, or in parallel. Once this potential parallelism is identified, the designer controls whether or not the parallelism is exploited. 

Allocates registers and memories to variables, and uses a clique partitioning algorithm to allow sharing. This clique partitioning algorithm gives priority to the least-connected vertices. 

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