HardwareC compiler

As a first step, the HardwareC compiler performs a profound data/control-flow analysis. A DFG optimizer is directly coupled to the compiler. After optimization, the data/control-fiow graph will be stored as a combined single flow graph which can be considered as a data base. All behavioral synthesis transformations require input from this data base and will produce output in the graph format defined in chapter 2. 

HardwareC supports a single-in, single-out control flow. This implies that no gotos, breaks from loops, and returns from procedures (other than at the very end) are allowed. It supports the usual iterative and branching control-flow constructs. Iteration can be specified eitha as fixed-bound loops (for loop) or data-dependent loops (while or repeat-until loops), depending on whether the loop exit condition is known at compile time. 

Behavioral transformations identify the parallelism in the HardwareC description using compiler optimization techniques. They also permit the designer to change the procedure calling hierarchy to conux)l the granularity of hardware sharing in subsequent synthesis steps. The BIF is used as the underlying representation for all transformations. 

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