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Gate Sizing During Timing-Driven Placement

Gate Sizing During Timing-Driven Placement [Pg.65]

A great deal of focus has been given specifically to the constmction of cheap, incremental methods for improving timing along critical paths in an optimized design. [Pg.65]

Papa and I. L. Markov, Multi-Objective Optimization in Physical Synthesis of Integrated Circuits, Lecture Notes in Electrical Engineering 166, [Pg.65]

Gate Sizing During Timing-Driven Placement... [Pg.65]

See other pages where Gate Sizing During Timing-Driven Placement is mentioned: [Pg.9]    [Pg.151]   


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