Fixed-size architecture design

In general, the regularized DG is still not suited to be mapped directly on hardware because it would result in a processor array of a size dependent on the parameters in the original description. This is, for instance, true for the Floyd-Steinberg demonstrator where the parameters M and N can vary over wide ranges. 

We have defined a design step partitioning-clustering [5, 6, 7] to decompose the regularized DG in a network of similar reduced-size DGs, called tiles. We call this network the tile graph. An alternative approach, based on the same principles but tuned towards latency-driven applications, is discussed in chapter 3. 

After partitioning, we have achieved a hierarchical decomposition of the DG in two DGs, the tile graph and the tile, both having a reduced and possibly 

the tiles are processed in parallel on a fixed-size processor array of which each processor executes the operations of a tile sequentially. Consequently, a processor of the array needs internal memory to store intermediate data of a tile. This scheme is used for increasing processor efficiency or slowing down I/O rate. 

This scheme works the other way around. Here, the tiles are sequentially processed on a fixed-size array that executes the operations of a single tile in parallel. It needs memory external to the array to store data for another tile. Typically, LPGS is used to execute huge and parametrized algorithms on a relatively small and fixed size array. 

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J. Bu and E. Deprettere. Processor clustering for the design of optimal fixed-size systolic arrays. Algorithms and Parallel VLSI Architectures, Vol. A, pages 341-362. North Holland, Elsevier, Amsterdam, 1991. 

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