Finite State Machine FSM Synthesis

Finite State Machine synthesis involves a number of steps. This section provides a description of the steps in DC after coding the source VHDL. 

Clock clock Sense rising edge Asynchronous Reset Unspecified 

Example 5.2 VHDL Code for FSM and Synthesis script package fsm states is 

Asynchronous Reset Unspecified Encoding Bit Length 4 Encoding style one hot 

Once the state machine is extracted, the design can be written out in state machine format or to the original RTL VHDL format by the following steps  

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