Enumeration type ambiguity

An ambiguous statement can arise if it is not possible to determine which enumeration type is being used. One consequence of this is tfiat the syntihesizer may not be able to determine which version of a subprogram is being called. This often occurs when a function or operator has been overloaded. Consider the package PARITY FUNCTIONS 2 shown below. 

Figure 3 Isomeric possibilities for structures for E Mx-n, n = (x — 1) — l,x = 4-6. Only the geometry of highest total vertex connectivity (usually denoted as closo but note the ambiguity for x = 4) and that of next highest (usually denoted as nido) are shown for economy of space. Likewise, only the binary E and M clusters are enumerated. Clearly, many more structures are possible if more open structures are allowed or more than one type of main group or transition metal element is used in the compound...

SUB" is an enumeration literal defined in type "CHARACTER" in the package "STANDARD" which is implicitly visible in all VHDL designs. Since this definition as well as the component declaration for "SUB" are both visible in the code, a homograph is reported. You can explicitly avoid this ambiguity as follows... 

As the above example demonstrates, ambiguous expressions that need qualifying usually occur because the same enumeration literal(s) occurs in more than one type declaration. 

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