Arithmetic processor interface

Figure 3. Schematic logic diagram of a hardware interface between a Zilog Z80A microprocessor and the Am9511A arithmetic processor unit.

Figure 4. Logic diagram of an Am9511A arithmetic processor unit to S-100 bus hardware interface.

The internal structure of the array processor comprises four functional units interconnected by internal buses (Fig. 6). The functional units are a host interface (which is system specific and provides communication with the host bus), a control processor (which controls the overall subsystem), a data memory (which acts as a data and table storage area), and a pipelined arithmetic unit (which... 

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