Transistor stack size

The number of complex gates were in the range of ll%-38% (22.8% on average). Also, savings of 30% in both gate and transistor count using a stack size restriction of (3,3) have been reported [1]. 

In the future it is supposed that the number of pixels per word-line and bit-line will be increased to more than 2048, and pixel size is reduced to less than 1/16. The delay for the conventional scheme will be of the order of 103 s whereas the proposed double word-line/bit-line scheme using stacked organic transistor sheets is estimated to reduce the delay by several order of magnitude. Power consumption... 

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