4-to-l multiplexer

The 4-to-l multiplexer selects an output Y from one of four inputs A, B, C or D based on the state of the two select lines SO and SI. The logical fimc-tion of the circuit is shown in Table 4.3 and a top-level block diagram showing the inputs and output is illustrated in Figure 4.1. 

Figure 4.3 Four variants of the 4-to-l multiplexer in a dataflow design style.

Figure 4.8 4-to-l multiplexer using only Nand gates. 

Figure 4.13 4-tO l multiplexer using optimum logic gates. 

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