Synthesizable constructs

Note that this is just one of several non-synthesizable constructs in Verilog HDL. See one of the references for either Verilog or VHDL. 

The compile off/on command also allows other non-synthesizable constructs to be implemented. 

To give an idea of what Verilog HDL constructs are synthesizable, this appendix provides a listing of the synthesizable Verilog HDL constructs that are recognized by the ArchSyn synthesis system, vl4.0. This subset may not be the same for all synthesis tools. 

Constructs that have relevance only to simulation, and not to synthesis, are identified as ignored constructs and constructs that are not synthesizable are marked as not supported . The constructs are categorized as follows ... 

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