Pre and Post-Synthesis Simulation

In this chapter, we discuss an example VHDL code, provide a testbench for the same example and the output files of the simulation performed using VSS. Two i proaches to simulation are discussed. The first approach is suited to an interactive simulation with waveforms, while the second involves reading the stimulus from a test file and writing the output to another file. 

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The synthesizer will ignore the actions associated with certain states and so pre- and post-synthesis differences will result in the simulation. 

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