NAND gate design

Fig. 26 (a) NAND gate design the resistance of Rvar will only drop below Rflxed when both inputs are charged, (b) DE NAND gate in action (Reproduced with permission from O Brien et al. 2010)... 

Fig. D.9. (a) Inverter, (b) NAND gate, and (c) NOR gate designs using complementary transistor elements. Complementary devices can be fabricated using n and p-type OFETs, or by combining p-type OFETs with another material, such as amorphous silicon, which produces NFETs.

Fig. 6 Design for a NAND gate formed via placement of dangling bonds on an otherwise hydrogen-passivated Si(lOO) surface. Data are input via the depassivation/repassivation of dangling bonds. Taken from Ref 26.

Renaud N, Joachim C (2008) Design and stability of NOR and NAND logic gates constructed with three quantum states. Phys Rev A 78 062316... 

In this section the results of the simulated training of voltage in -current out NanoCells are presented. Using this design, several complex, negating logic gates were trained, many of them easily. Except for the four NANDs and the 1 -bit adder, all of these NanoCells were trained with the version of the simulator that worked with IsSpice. 

Zhou J, Arugula MA, Halmnek J, Pita M, Katz E. Enzyme-based NAND and NOR logic gates with modular design. J Phys Chem B 2009 113 16065-16070. 

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