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MiniMIPS microprocessor

Table 4.5 shows the size and performance of the implemented processor and the hardware module. The hardware module implementation has a total of 128 registers. It was not protected against SEEs because of the fact that the worst case scenario is an incorrect fault detection, which would not compromise the system. The implemented hardware module occupies 15 % of the total area of the miniMIPS microprocessor, while maintaining the same operating frequency. It is important to note that the hardware module has a fixed size, independent of the processor being used. That means that a bigger processor would lead to a smaller hardware module percentage, when compared to the processor. [Pg.60]

Table 4.6 OCFCM technique area results for a set of applications and the percentage of the area compared to the miniMIPS microprocessor synthesized into FPGA... Table 4.6 OCFCM technique area results for a set of applications and the percentage of the area compared to the miniMIPS microprocessor synthesized into FPGA...
The experiment eontinuously compared the PC of a golden miniMIPS with the PC of the faulty one. Fault injection results are presented in Table 5.3. It shows the number of iqected faults (Faults Injected) for each application, the number of faults that caused an error to the microprocessor (Incorrect Result) and the detection rate achieved by the proposed solution (Errors Detected). The system was simulated with a clock period of 42 ns and a total of 2459 signals describing it. Forty thousand faults represent 16 times the number of signals, but only 0.4 % of the extensive pos-sibihties of faults for the encryption algorithm... [Pg.81]


See other pages where MiniMIPS microprocessor is mentioned: [Pg.27]    [Pg.28]    [Pg.100]    [Pg.27]    [Pg.28]    [Pg.100]    [Pg.27]    [Pg.81]    [Pg.95]    [Pg.96]   
See also in sourсe #XX -- [ Pg.13 , Pg.45 , Pg.58 ]




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