Memory/adder model

A memory/adder model based on an electromechanical single... 

Based on this design a memory/adder model (Fig. 6(c)) using 464 transistors could be constructed and evaluated on grounds of SPICE circuit simulations. Four bits of information were read from four different memory cells, added as two 2-bit words, and the resulting 2-bit was moved through registers (clocked D-latches) to a subsequent computation. It must be noted... 

The examples were run on an IBM Rise System/6000 Model 520 workstation with 40Mb of memory. The results for scheduling are summarized in Table 1. No explicit constraints were given to obtain the shortest number of cycles on all paths, with the exception of ELLIPTF (FUs limited to 1 multiplier and 2 adders), MAHA (FUs limited to 1 adder and 1 subtracter) and DIFFEQ (FUs... 

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