Datapath

New data paths to accommodate FM synthesis The datapath is shown in figure 5.7. 

Quite often, a synthesis tool might automatically preserve the hierarchy of a large datapath operator. For example,... 

PipeRench is designed as a virtualized programmable datapath for media... 

Ugurdag, H. F. Fuhrman, T. E. (1996), Autocircuit A clock edge general behavioral system with a direct path to physical datapaths, in Proc. ICCD 96 , pp. 514-523. 

It should be noted that even as the asynchronous communication of ProcVhdl may be embedded in Vhdl s event-based semantics, it may also be built on top of synchronous hardware. In fact, a likely implementation of a ProcVhdl functional unit is a synchronous finite state machine with an attached datapath. 

The output of Amical is a structure composed of two subsystems a datapath and a controller. This RTL specification is generated in two steps. The first produces an abstract architecture coded in an intermediate form called SOLAR [7]. In order to reach silicon, this abstract architecture needs to be refined in order to include a synchronization scheme (clocks, resets) and other characteristics such as testing. This refinement produces a detailed architecture specification. During the last step, glue cells may be inserted. For example, a synchronization block may be included anywhere in the circuit hierarchy, if such a personalized scheme is needed. This may be useful in the case of a... 

The final output of Amical is a netlist composed of a control unit and a datapath. The data-path is itself a netlist. The controller is an FSM description that can be fed to an FSM synthesizer such as that described in chapter 10. 

Control That part of the processor that controls itself and the datapath of the processor. 

Datapath The components of the datapath may include registers, arithmetic and logic unit (ALU), shifter, bus. 

The computer architect must determine the algorithm to be used in performing an arithmetic operation and mechanism to be used to convert from one representation to another. Besides the movement of data from one location to another, the arithmetic operations are the most commonly performed operations as a result, these arithmetic algorithms will significantly influence the performance of the computer. The ALU and Shifter perform most of the arithmetic operations on the datapath. 

This sequential circuit is the fastest and most expensive part of the memory hierarchy. The registers are the part of the memory hierarchy that are directly a part of the processor datapath. Because these are the fastest memory it is desirable to have all of the active data present in them. 

The implementation of the instmction set through the design of the datapath and control within the processor... 

A.C. Parker, J. Pizarro, and M. Mlinar, MAHA A Program for Datapath Synthesis, Proceedings of the 23rd Design Automation Conference, pp. 461-466, Las Vegas, Jime 1986. 

Jain, H. De Man, and J. Vandewalle, General Datapath, Controller and Inter-Communication Architectures for the Creation of a Dedicated Multi-Processor Environment , Proc. of ISCAS 86, pages 730-732, May 1986. 

Neerav Berry and Barry M. Pangrle, Schalloc An Algorithm for Simultaneous Scheduling Connectivity Binding in a Datapath Synthesis System , Proc. ofEDAC 90, pages 78-82, March 1990. 

The Univ. of Illinois IBA (Interleaved binder and Allocator) system consists of several parts Illinois Mixed behavior / Structure Language (IMBSL), which performs data path synthesis RLEXT (Register Level Exploration Tool), which allows a user to manually modify a Register-Transfer level design, and then automatically repairs any errors or omissions so that the final result matches the specified behavior, COD, a control unit synthesizer LE (Layout Estimator) and Fasolt, a Register-Transfer level datapath optimizer. See also Univ. of Southern California s ADAM System — Knapp used to be involved with that stem. 

David W. Knapp, Feedback-Driven Datapath Optimization in Fasolf, iVoa ofICCAD 90, pages 300-303, November 1990. 

David W. Knapp and Marianne Winslett, A Formalization of Correctness for Linked Representations of Datapath Hardware , in Formal VLSI Specification and Synthesis,... 

David W. Knapp, Manual Rescheduling and Incremental Repair of Register-Level Datapaths , Proc. of ICCAD 89, pages 58-61, November 1989. 

DW also provides the capability for users to create their own DW libraries. In addition to re-use, these user built libraries provide a very effective mechanism to infer structures that DC would not normally map to via compile. This is veiy useful, especially when dealing with complex datapath structures. The concept of design re-use and parts available in the DW library are discussed in greater detail in Chapter 10. 

You have two clocks in your design CLK1 (20 ns clock period) and CLK2(10 ns clock period). There are datapaths in the design between the two clock domains. The functionality of the design is such that the clock domain CLK2 captures new data only when CLK1 is low. How is the information passed on to DC for optimization ... 

In designs where there are multiple clock domains and datapaths between the clock domains, TC will place clocks in separate capture clock groups, provided they are independent clocks sources in the testmode and not multiplexed to one test clock. Further, the clock skew must be accounted for in the clock waveforms. 

In this case, TC infers two clocks, dk1 and clk2, in the testmode. If the test clock waveforms are specified taking into account the skew (after checking the skew of the clocks with the ASIC vendor), TC will be able to identify the illegal paths on the datapaths and place the clocks in different capture clock groups. Hence, in Figure 8.2, if we change the waveform of the clock dk1 from the default as follows ... 

You have several implementations of a certain datapath module (say an adder.) You wish to use a different implementation (the most appropriate with regard to speed and area) in each instance of an adder in the design. For example, you wish to use a cany select adder in one block, but a ripple carry implementation of the same adder in another. 

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